1. Field of the Invention
The present invention relates to a method for processing an address parity error that has occurred in accessing a memory, and also to an apparatus and a storage which each have a function for realizing the method.
2. Description of the Related Art
Generally, in information processors, such as a computer system, which each include a storage (memory), an error check is performed using an address with a parity bit attached (hereinafter called an parity-bitted address) in accessing the memory. Also, the data is stored in the memory under the protection of the error checking and correction (ECC) function; if an error (1-bit error) is detected in the data read out from the memory, a process for correcting the detected error is performed.
An example of such an ordinary information processor will now be described with reference to FIG. 9. FIG. 9 is a block diagram showing the information processor equipped with an accessing unit 10 and a storage 20.
The accessing unit 10 comprises an write data generator 11, an address generator 12, a parity generator (PG) 13, a control signal generator 14, a read data receiver 15, and an error signal receiver 16, which are provided by a CPU, for example.
The storage 20 has a memory (MEM) 21 storing various types of data, a parity checker (PC) 22, a check bit generator (CG) 23, an error checker 24, and a 1-bit error correcting circuit 25.
The write data generator 11 generates the data to be written into the memory 21 in having access to the memory 21 to write (hereinafter interchangeably called xe2x80x9cwrite-accessingxe2x80x9d or xe2x80x9cdata writing processxe2x80x9d).
The address generator 12 generates an address of an access destination in accessing the memory 21.
The parity generator 13 generates a parity bit for the address generated by the address generator 12 and attaches the generated parity bit to the generated address.
The control signal generator 14 generates a control signal instructing the memory 21 to perform write-accessing or read-accessing.
The read data receiver 15 receives the data read out from the memory 21 in having access to the memory 21 to read (hereinafter interchangeably called xe2x80x9cread-accessingxe2x80x9d or xe2x80x9cdata reading processxe2x80x9d).
The error signal receiver 16 receives an error signal from the parity checker 22 and the error checker 24 (will be described later).
The parity checker 22 makes a parity check over the parity-bitted address from the accessing unit 10. If an address parity error is detected, the parity checker 22 notifies the accessing unit 10 (error signal receiver 16) of the error detection as an error signal.
The check bit generator 23 generates an error-correcting check bit corresponding to the data from the accessing unit 10 (write data generator 11) and writes to the memory 21 both the generated error-correcting check bit and the last-named data.
The error checker 24 produces and outputs a syndrome code (ECC code) based on both read data from the memory 21 and the error-correcting check bit for the read data in read-accessing to the memory 21. The syndrome code indicates whether or not an error appears in the read data and the type of the error, or which one of a 1-bit error and an uncorrectable error it is. If a single bit is in error (1-bit error), the syndrome code also includes the information as to which bit is in error (to be corrected). The syndrome code is sent to the 1-bit error correcting circuit 25 and the accessing unit 10 (error signal receiver 16) as an error signal. In this instance, the uncorrectable error is exemplified by a multi-bit error, in which two or more bits of the read data from the memory 21 are in error.
If a single bit is in error (1-bit error) in the read data, the 1-bit error correcting circuit 25 corrects the bit before sending the read data to the accessing unit 10 (read data receiver 15). At that time, if the error checker 24 detects a correctable error or a 1-bit error, the 1-bit error correcting circuit 25 specifies which bit to correct (an error bit) based on the syndrome code from the error checker 24, and corrects the read data by inverting the error bit. Contrarily, if no error is detected by the error checker 24, the read data passes through the 1-bit error correcting circuit 25 and is sent to the accessing unit 10 (read data receiver 15).
In the above information processor, the accessing unit 10 takes access to the memory 21 based on both the address generated by the address generator 12 and the control signal generated by the control signal generator 14.
Specifically, in write-accessing, the control signal generator 14 outputs to the memory 21 a control signal giving an instruction for writing-in. Then the write data, which is generated by the write data generator 11, and the check bit, which is generated by the check bit generating circuit 23 based on the last-named write data, are written to the memory 21 in the address, which is generated and designated by the address generator 12.
On the contrary, in read-accessing, the control signal generator 14 outputs to the memory 21 a control signal giving an instruction for reading-out. Then the data stored in the memory 21 in the address generated and designated by the address generator 12 is read out as the read data.
If the error checker 24 detects an error (1-bit error/uncorrectable error) in the read data, the error detection is notified to the accessing unit 10 (error signal receiver 16) as an error signal (syndrome code).
Upon occurrence of a 1-bit error, the 1-bit error correcting circuit 25 corrects the read data based on the syndrome code from the error checker 24, and the corrected read data is then sent to the accessing unit 10 (read data receiver 15). If no error is detected, the read data passes through the 1-bit error correcting circuit 25 and is then sent to the accessing unit 10 (read data receiver 15).
The parity bit generated by the parity generator 13 is attached to the address, which is generated by the address generator 12. The address is then transmitted to the storage 20, whereupon the parity checker 22 makes a parity check over the address using the parity bit.
If an address parity error occurs, it is unclear to which address in the memory 21 accessing should take place. Accordingly, upon detection of the address parity error by the parity checker 22, the error detection is notified to the accessing unit 10 (error signal receiver 16) as an error signal.
Upon receipt of the error signal from the parity checker 22 by its error signal receiver 16, the accessing unit 10 interrupts, during the process being currently made, to immediately perform a recovery process (error analysis or retry).
However, even if a recovery process is made immediately after the occurrence of the address parity error in write-accessing and then the write data is written into the memory 21, the write data becomes useless unless read accessing to the last-named write data is performed by the accessing unit 10, thus making the recovery process also useless.
Since a recovery process takes a relatively long time period, the processing efficiency and throughput of the accessing unit 10 would be reduced because such time-consuming recovery process is performed every when the address parity error occurs in write-accessing.
One object of the present invention is to provide an address parity error processing method in which the processing efficiency and throughput are improved by performing only a necessary recovery process that is required in read-accessing to a memory even when an address parity error has occurred in write-accessing to the memory.
Another object of the invention is to provide an apparatus for carrying out the above-mentioned method.
Still another object of the invention is to provide a storage for use in carrying out the above-mentioned method.
In order to attain the above second-named and third-named objects, there is provided an apparatus/storage comprising: a first selector for selecting one of write data and a parity-bitted address (an address with a parity bit attached) for writing to the memory. If an address parity error has been detected as the result of the parity check made by the parity checker in write-accessing to the memory, the first selector is operative to select the parity-bitted address, in which the address parity error has occurred, for writing the selected address, instead of writing the write data, to the memory during the write-accessing.
In order to attain the above first-named object, in the apparatus/storage, a parity check is made over the parity-bitted address generated in write-accessing to a memory. If an address parity error has been detected as the result of the parity check, the parity-bitted address, in which the address parity error has occurred, is written to the memory, thus realizing the address parity error processing method according to the present invention.
As one preferred feature, upon occurrence of an address parity error, only the address in place of the write data, which would not be used until being read out, is written to the memory. After that, if the parity-bitted address, in which the address parity error has occurred, is read out from the memory in read-accessing, a recovery process is performed for the address parity error. In this manner, only a required recovery process can be performed in read-accessing to a memory, even when an address parity error has occurred in write-accessing to the memory, thus making it possible to save unnecessary recovery processing if data about the address parity error is not used.
As another preferred feature, an error checker is provided to detect the address parity error based on an error-correcting check bit for the data to be read out, making it possible to recognize in the read-accessing that the parity-bitted address, in which the address parity error has occurred, is read out.
The detection of an address parity error by the error checker is realized by the following exemplified construction:
(1) changing means changes an error-correcting check bit, which is to be written to the memory along with an address. If the address is then read back in read-accessing, the error checker produces a syndrome code indicating an uncorrectable error. With this construction, when the address, in which the address parity error has occurred, is read out from the memory, the error checker can detect the uncorrectable error. At that time, the changing means can be easily realized in the form of a circuit for inverting the bit data of the error-correcting check bit to be written to the memory.
(2) upon occurrence of an address parity error, an error-correcting check bit, which allows the error checker to produce a syndrome code that can specify the address parity error, is written to the memory. With this construction, upon read-out of the address in which the address parity error has occurred, the error checker can immediately recognize that the read data is related with the address parity error.
As still another preferred feature, the apparatus further comprises a judging section for discriminating, upon detection of an address parity error in accessing to the memory, whether or not the address parity error is due to a parity bit. If, using the judging section, an address parity error due to any other reason than a parity bit is detected in write-accessing to the memory, the parity-bitted address, in which the address parity error has occurred, is written to the memory. In the meantime, if an address parity error due to a parity bit is detected, the write data is written to the memory as it is.
With this construction, if only a parity bit is in error but with no error in address data, the write data is written to the memory as normal. On the contrary, if an error has occurred in the address data, the address, in which the address parity error has occurred, is written therein.
As a further preferred feature, if an address parity error is detected in read-accessing to the memory, the parity-bitted address, in which the address parity error has occurred, is output, instead of the read data to be read out from the memory, during the read-accessing thereto, thus enabling an immediate error analysis based on the address.
At that time, if, using the judging section, an address parity error due to any other reason than a parity bit is detected in read-accessing to the memory, the parity-bitted address, in which the address parity error has occurred, is output as the read data. In the meantime, if an address parity error due to a parity bit is detected, the read data is read out to be output as it is.
With this construction, if only a parity bit is in error but with no error in address data, the read data is read out from the memory as normal. On the contrary, if an error has occurred in the address data, the address, in which the address parity error has occurred, is output as the read data.
In this instance, two or more parity bits are generated and attached to an address, thus causing a parity bit multiplication. Based on whether or not the plural parity bits are identical, the judging section is able to discriminate whether or not the address parity error is due to the parity bits.
According to the address parity error processing method, the apparatus, and the storage of the present invention, it is possible to guarantee the following advantageous results:
(1) Only a necessary recovery process required in read-accessing to a memory is performed even when an address parity error has occurred in write-accessing to the memory. Namely, since no recovery process such as an error analysis or retry is made for the address parity error unless the data about the address parity error is used, unnecessary recovery processes can be saved, thus greatly improving the processing efficiency and throughput in the apparatus, such as a computer system. Further, the address written to the memory (the parity-bitted address in which the address parity error has occurred) facilitates the error analysis.
(2) It is possible to realize with ease the above-mentioned functions and results by simply adding to an existing apparatus or storage a selector as hardware.
(3) In read-accessing to the memory, it is possible to recognize, using an error-correcting check bit, that the parity-bitted address, in which the address parity error has occurred, is read out from the memory and then to immediately moves the procedure to a recovery process for the address parity error.
(4) At that time, changing means damages the error-correcting check bit to generate a syndrome code indicating an uncorrectable error, thus making it possible to recognize the read-out of the address, in which the address parity error has occurred, as the occurrence of the uncorrectable error.
(5) And, the error-correcting check bit is used to generate a syndrome code which specifies the address parity error, thus making it possible to immediately recognize that the read data from the memory is related with the address parity error. In this case, the generating the syndrome code based on the check bit can be realized with ease by utilizing an existing error checking and correction (ECC) function with changes in software only added.
(6) Only when an error appears in address data, the address, in which the address parity error has occurred, is written to the memory. Therefore, with no address data bit in error, a write process is performed as normal to save unnecessary recovery processing, thus further improving the processing efficiency and throughput.
(7) If an address parity error is detected in read-accessing to the memory, the parity-bitted address, in which the address parity error has occurred, is output instead of the read data. Accordingly an error analysis can be immediately performed based on the address and a recovery process such as retry can also be made without delay, thus improving the processing efficiency.
(8) Only when an error appears in address data, the address, in which the address parity error has occurred, is output as the read data. Therefore, with no address data bit in error, a read process is performed as normal to save unnecessary recovery processing, thus further improving the processing efficiency and throughput.
Other objects and further features of the present invention will be apparent from the following detailed description when read in conjunction with the accompanying drawings.